1. Field of the Invention
The present invention relates to hermetically sealed semiconductor chips. More specifically, the present invention relates to a fully hermetically sealed semiconductor chip and its method of manufacture.
2. Description of the Related Art
Solid state electronic devices, or semiconductor chips, are typically manufactured from a semiconductor material, such as silicon, germanium, or gallium/arsenide. Circuitry is formed on one surface of the device with input and output pads being either formed around the periphery or generally in the center of the device to facilitate electrical connection.
The semiconductor chips are typically packaged to protect the chip from mechanical damage, external contamination, and moisture. Typical semiconductor chip packages may be divided into the broad categories of plastic encapsulated type, quasi-hermetic cavity type and fully hermetic cavity type. While plastic-encapsulation of semiconductor chips is the most common form of packaging chips, the plastic encapsulation allows the chip to be vulnerable to electrochemical processes. The numerous and extensive polymer/metal interfaces in the plastic encapsulated semiconductor package affords ample opportunities for moisture ingress as well as allowing the soluble ions present to provide an electrolyte for the corrosive failure mechanism of the semiconductor chip. Also, the extensive use of precious metals coupled with base metals in chips and packages provides dc galvanic potentials for electrochemical corrosion reactions and dendrite growth, thereby affecting the performance and life of the encapsulated semiconductor chip.
As a result of the problems associated with the plastic encapsulation of semiconductor chips, it is desirable to hermetically package chips to prevent external moisture and chemicals from contacting a chip. Hermetic packages for semiconductor chips generally are of the metal and ceramic material type. The common feature shared by these packages is the use of a lid or a cap to seal the semiconductor device mounted on a suitable substrate. The leads from the lead frame also need to be hermetically sealed. In metal packages, the individual leads are sealed into the metal platform by separated glass seals. In ceramic packages the leads are commonly embedded in the ceramic itself.
Several types of ceramic packages are used to hermetically seal semiconductor chips. Typically, such types of hermetic packages are ceramic dual-in-line package, hard glass package, side-brazed dual-in-line package, bottom-or top-brazed chip carrier, pin-grid array or other multilayer ceramic package. Some of such types of packages are described in U.S. Pat. No. 4,769,345, 4,821,151, 4,866,571, 4,967,260, 5,014,159, and 5,323,051.
However, such prior art type hermetically sealed packages for semiconductor chips all use an external package formed around the chip to form the hermetic seal. Such external packages increase the size and cost of the semiconductor chip for installation of the chip with associated circuitry.
While it is well known to attempt to seal semiconductor chip active circuitry at the wafer stage of production by applying a passivation coating to the wafer with ceramic materials such as silica and/or silicone nitride by CVD techniques, the subsequent etching back of the passivation coating at the bond pads of the semiconductor chip damages the passivation coating around the bond pads, thereby affecting the reliability of the chip and shortening the life of the chip from environmental corrosion, as such chips are not truly hermetically sealed or considered to be fully hermetically sealed chips.
In an attempt to hermetically seal semiconductor chips without the use of external packages, in U. S. Pat. Nos. 4,756,977 and 4,749,631 it has been suggested to use lightweight ceramic protective coatings on such chips derived from hydrogen silsesquiozane and silicate esters as well as additional ceramic layers as hermetic barriers.
In another attempt to hermetically seal semiconductor chips without the use of external packages, as disclosed in U. S. Pat. No. 5,481,135, when certain ceramic protective coatings, such as those derived from hydrogen silsesquiozane and silicate esters, are applied to the active surface of a semiconductor chip at the wafer level, even though the bond pads are subsequently exposed by removing a portion of the ceramic protective coating, the resultant circuits remain hermetically sealed. However, the use of such ceramic protective coatings applied to the semiconductor chip at the wafer level are applied only to the active circuitry side of the wafer, not both sides of the wafer, nor on the edges of the semiconductor chips. As such, the semiconductor chip is not truly or fully hermetically sealed. At best, only one side of the semiconductor chip may be thought to be hermetically sealed, thereby leaving the other side of the chip unsealed as well as the edges of the chip.
None of the prior art hermetically sealed semiconductor chips described hereinabove are fully hermetically sealed without the use of a separate package, either metal or ceramic. A need exists for a fully hermetically sealed semiconductor chip which is fully hermetically sealed on both sides and the edges thereof without the use of a separate package.
The present invention relates to hermetically sealed semiconductor chips. More specifically, the present invention relates to a fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.